1. Field of Invention
The present invention generally relates to a power layout method and structure of a main bridge chip substrate and a motherboard, and more particularly, to a power layout structure of a 4 layers main bridge chip substrate and a motherboard, so that the main bridge chip can stably operate under the frequency needed by high speed components.
2. Description of Related Art
Accompanying the fast development of new technology, the operating speed of computers is getting faster. Using the Intel Pentium 4 processor as an example, the speed of the CPU bus can reach as high as 532 MHz (133 MHz×4). In contrast, the main bridge chip must provide higher speed on other buses to communicate with the peripheral devices that are coupled to the main bridge chip. These buses comprise the 333 MHz memory bus (166 MHz×2), the 528 MHz AGP bus (66 MHz×8) and the 528 MHz main-subaltern bridge bus (66 MHz×8). In designing the main bridge chip, not only does the high speed operation mentioned above have to be achieved, but the layout of the main bridge chip substrate and the motherboard also have to provide stable operation for the components mentioned above. Usually, there are some basic design procedures that need to be followed in designing the circuit layout of the main bridge chip substrate and the motherboard. For example, in order to stabilize the signal quality on the signal layer, a grounded layer contiguous to the signal layer has to be provided on the main bridge chip substrate and the adjacent motherboard, so that all signals on the signal layer can refer to the grounded layer.
The conventional layout method of the main bridge chip substrate and the motherboard usually generates some signal referrencing problems. FIG. 1 schematically shows a circuit layout of the motherboard and the main bridge chip substrate in the prior art, from up to down it sequentially comprises a top signal layer 11, a grounded layer 12, a power layer 13, and a bottom solder layer 14. In the conventional layout of the motherboard and the main bridge chip substrate, almost all signals are placed on the top signal layer 11, so that all signal lines can refer to the grounded layer 12. On the other hand, different power supplies can be provided by layout and partitioning the power layer 13. Furthermore, the bottom solder layer 14 on the main bridge chip substrate not only provides the solder ball to solder the components on the motherboard, but also provides a place for a small portion of the signal lines that do not need high signal quality. However, when the main bridge chip demands an operating speed with higher frequency (such as more than 1 GHz), since the related controller and interface will consume more power, the layout of the main bridge chip substrate and the motherboard becomes more and more important, and the power layout is the most important topic to be conquered.
FIG. 2 schematically shows a plane of the power layout 200 for the main bridge chip on the power layer 13 of the conventional motherboard. The partition situation of the power layer 13 is also shown in FIG. 2. Furthermore, FIG. 2 also depicts many bonding pads. The bonding pads are located on the top signal layer 11, and couple to the power layer 13 through a via. To be noted, the arrangement of the bonding pads is determined according to the position of related components on the motherboard. The main bridge chip substrate couples to the bonding pad on the motherboard via the solder ball that is placed on the bottom solder layer 14, so that the main bridge chip can obtain the related operating voltage to support its operation.
FIG. 2 further comprises a plurality of working connection areas. The CPU working connection area 201 denotes an area where the bonding pads are located, wherein the bonding pads are used to couple the main bridge chip to the CPU. Besides the signal bonding pads that are coupled to the CPU, it also comprises several grounded bonding pads (the black solid circle) and the CPU power bonding pads (marked as “T”). The CPU power ring 201A denotes a portion that is located within the CPU working connection area 201 and is coupled to the CPU power bonding pads in the power ring of the main bridge chip. Moreover, the memory working connection area 202 denotes an area where the bonding pads are located, wherein the bonding pads are used to couple the main bridge chip to the memory. Besides the signal bonding pads that couple to the memory (such as SDRAM), these bonding pads also comprise several grounded bonding pads and the memory power bonding pads (marked as “M”). The memory power ring 202A denotes a portion that is located within the memory working connection area 202 and is coupled to the memory power bonding pads in the power ring of the main bridge chip. Furthermore, the subaltern bridge working connection area 203 denotes an area where the bonding pads are located, wherein the bonding pads are used to couple the main bridge chip to the subaltern bridge. Besides the signal bonding pads that couple to the subaltern bridge, these bonding pads also comprise several grounded bonding pads and the subaltern bridge power bonding pads (marked as “V”). The subaltern bridge power ring 203A denotes a portion that is located within the subaltern bridge working connection area 203 and is coupled to the subaltern bridge power bonding pads in the power ring of the main bridge chip. The AGP working connection area 204 denotes an area where the bonding pads are located, wherein the bonding pads are used to couple the main bridge chip to the AGP device. Besides the signal bonding pads that couple to the AGP device, these bonding pads also comprise several grounded bonding pads and the AGP power bonding pads (marked as “A”). The AGP power ring 204A denotes a portion that is located within the AGP working connection area 204 and is coupled to the AGP power bonding pads in the power ring of the main bridge chip. The central portion of the circuit layout 200 is the grounded bonding pad area 206. To be noted, the grounded bonding pad and the signal bonding pad in FIG. 2 are denoted with a black solid circle 207 and a while hollow circle 208 respectively.
Although the conventional power layer 13 uses the layout in FIG. 2 for plane partition, as a matter of fact, the power plane after the portioning can not be fully utilized. For example, the area 205 depicts the power path that is the one physically used by the CPU working connection area 201. Since the power path 205 cuts into one side of the CPU working connection area 201, the distribution of the inductance on both sides of the CPU working connection area 201 is not even, resulting in the instability of the power voltage. In other words, the CPU that is far from the power path 205 has higher inductance and the CPU that is near the power path 205 has lower inductance, so the power voltage is not so stable. Moreover, from the power layout in FIG. 2, the width layout of the power ring 201A, 202A, 203A, and 204A on the power layer 13 is not so even. For example, the area that is denoted by the area 202B and 202C have different widths, thus forming a gap of the angles, and these areas have higher inductance. Therefore, in the operation under high speed, the power layer 13 cannot usually provide an immediate current. Consequently, a great ground/bounce effect is generated on the power layer 13, resulting in the instability of the entire high frequency signal, and causing the entire system to malfunction.